The present invention relates to bus snoop method and apparatus and more particularly to bus snoop method and apparatus which can lessen the influence of a low speed bus and give full play to the high-speed capability of a high speed bus in a computer system in which the low speed bus is coupled to the lower hierarchy of the high speed bus.
Generally, a CPU, a main memory unit, an external bus master and an I/O device are coupled to each other through a high speed bus and the I/O device is coupled to external peripheral units through a low speed bus. In this case, when the CPU accesses the I/O device to make a request to it for any data, the I/O device operates at a low speed and therefore the CPU must remain in a standby state until it receives data from the I/O device through the high speed bus and the high speed bus is occupied by the CPU during this standby condition. Accordingly, when the external bus master, for example, tries to access the main memory unit for the sake of transferring data, the accessing is not permitted during the occupation of the high speed bus by the CPU.
Especially, in a case where the CPU is a CPU with a cache and the bus master is provided with a direct memory access (hereinafter referred to as DMA) controller, an address and data recorded in the cache memory must always be coincident with the contents stored in the main memory unit. Therefore, in the past, when the DMA controller rewrites data at an address in the main memory unit, a snoop the procedure for snoop is taken each time a rewrite operation is carried out to check that the data at the address is transferred to the cache memory and if the transfer is completed, the address and the corresponding data are canceled. This control processing will hereinafter be called a snoop processing.
However, during the occupation of the high speed bus by the CPU, the snoop processing to be effected each time data of the main memory unit is rewritten cannot be executed. Consequently, a rewrite of data into the main memory unit due to access by the DMA controller remains in a standby state until the occupation of the high speed bus by the CPU is released, and after the occupation by the CPU is released, the data rewrite operation is executed and at the same time the snoop processing is executed, thus failing to make full use of the high-speed performance inherent to the high speed bus.
In order to avoid the above disadvantage of the cache memory snoop scheme, an example of an improved cache memory snoop scheme as described in JP-A-4-101251 has been proposed. According to this proposal, each time that access other than a rewite access to the main memory unit takes place, for example, a reading of data from the main memory unit or access to another memory unit than the main memory unit, which does not involved a snoop operation to the cache memory, data transfer is executed through a high speed bus without carrying out the snoop processing; however for data transfer needed for a data rewrite to the main memory unit which requires the snoop processing, a release of the occupation of the high speed bus by the CPU is waited for and after the release is completed, the snoop processing is executed.
In the conventional cache memory snoop scheme, a snoop generation circuit always monitors the state of the system bus and when an instruction for a data write operation is issued from the external bus master or DMA controller, it is detected whether an address for writing of the data is included in an address area targeted for the cache memory and only when the accessed address is included in the cache target area, a snoop signal is rendered to be active to execute the snoop processing to the cache memory. According to this scheme, however, when an instruction for writing data into the cache target area occurs, execution of the instruction is effected after the occupation of the high speed bus by the CPU is released, with the result that not only the high-speed capability of the high speed bus cannot be utilized sufficiently, but also data supplied externally during standby of the CPU is accumulated in the I/O device and the I/O device is sometimes caused to overrun; and besides, when data transfer due to DMA is executed through a period other than the period for the occupation of the high speed bus by the CPU, interference sometimes occurs between the I/O device and the CPU with cache, thus raising a problem that the throughput of the I/O device is degraded.